The present invention generally relates to integrated circuits, and more particularly, to an integrated circuit performing a logical function.
The Exclusive OR (XOR) logical function contains what is known in the art as a xe2x80x9cfunction hazardxe2x80x9d. Review of an XOR Karnaugh map shows that a circuit performing a logical XOR function cannot transition from a stable xe2x80x9c1xe2x80x9d state to the other stable xe2x80x9c1xe2x80x9d (or from a stable xe2x80x9c0xe2x80x9d state to the other stable xe2x80x9c0xe2x80x9d state) without passing through the xe2x80x9c0xe2x80x9d state (or xe2x80x9c1xe2x80x9d state) first. This function hazard is part of the XOR logical function and is not a logical hazard, which can arise from poor implementation of a logical function that is free of function hazards. As such, a function hazard results when a logic function transitions between nonadjacent squares of a Karnaugh map. In contrast, a logic hazard is not caused by the output function of the logical operation, but rather the configuration of the circuit to implement the function. For example, the output signal for a combinational circuit that depends on the internal circuit delays, both element and interconnection, as well as the input signals, the combinational circuit is said to contain a logic hazard. As a result, the combinational logic circuit may produce a momentary change in an output signal in response to an input change that does not cause the steady-state output to change or if the output signal is supposed to change it is possible for the output signal to change several times before settling down to its steady-state value.
The XOR function hazard often creates a false output from an XOR logic circuit that can cause a downstream edge-triggered logic circuit or gate to evaluate prematurely. Traditionally, the XOR function hazard is mitigated by adding additional logic elements to the output of the logic circuit performing the XOR logical function to either delay or gate the circuit""s output. These logic elements act like a filter to help avoid having downstream logic elements from evaluating invalid data or evaluating prematurely. Because integrated circuit surface area and operating speed are at a premium, the conventional technique for mitigating the detrimental effects of the XOR function hazard are an undue burden on an integrated circuit architecture.
The present invention addresses the above-described limitations of a logical circuit that performs the XOR logical function in order to simultaneously compare two or more bit pairs, for example, two or more complimentary dual rail bit pairs. The present invention provides an approach to enable a circuit performing a logical XOR function to avoid the XOR function hazard altogether.
In one embodiment of the present invention, an integrated circuit provides a static to dynamic converter circuit that receives a plurality of static input signals and generates a plurality of dual-rail domino output signals. Each of the dual-rail domino output signals have true and complement data components. The manner in which the static to dynamic converter circuit generates the dual-rail domino outputs allows an XOR logic circuit to avoid the XOR function hazard. The integrated circuit also includes an XOR logic circuit coupled to the outputs of the static to dynamic converter circuit. The XOR logic circuit performs a logical XOR function on two or more pairs of the dual-rail domino output signals from the static to dynamic converter circuit. The static to dynamic converter circuit includes a number of cross-coupled circuits where each cross-coupled circuit receives a static logic signal and a clock signal. The clock signal synchronizes operation of each cross-coupled circuit. Each cross-coupled circuit utilizes an implied inversion technique to prevent the static to dynamic converter from asserting an invalid output state.
The XOR logic circuit includes a plurality of dual-rail dynamic logic circuits each without a series evaluate transistor or xe2x80x9cfooterxe2x80x9d device. Each dual-rail dynamic logic circuit is configured to have a first pull-down stack and a second pull-down stack coupled in parallel between a ground node and a dynamic node. The first pull-down stack and the second pull-down stack perform the logical XOR function on a pair of dual-rail domino output signals asserted by the static to dynamic converter circuit.
The above-described approach benefits a semiconductor device, such as a microprocessor that has to compare two or more logic values in a simultaneous manner. As a result, an XOR logic circuit can be used to generate a xe2x80x9cfinishxe2x80x9d signal, which, in turn, can be used to start evaluation of the next stage in a data pipeline without the need for additional circuitry to gate or delay the finish signal to prevent a false start.
In accordance with another aspect of the present invention, a method is performed in an integrated circuit to avoid the function hazard of the logical XOR function. The integrated circuit avoids the XOR function hazard by generating pairs of dual-rail domino output signals from pairs of static input signals in a manner to avoid an unstable state in the logical XOR circuit that causes the XOR function hazard. Each dual-rail domino output signal pair generated is a monotonically rising signal encoded with a third valid state. The integrated circuit performs the logical XOR function on pairs of the dual-rail domino output signals in the logical XOR circuit. The pairs of dual-rail domino output signals generated by the method includes at least a first complementary dual-rail domino signal and a second complementary dual-rail domino output signal to drive the logical XOR circuit. Because the first and the second complementary dual-rail domino output signals are monotonically rising signals encoded with three valid states, the logical XOR circuit is able to transition from a first stable state to a second stable state without having to transition through an unstable state. Hence, the method performs a logical XOR function in an integrated circuit that allows the logical XOR circuit to transition from a first logic xe2x80x9c1xe2x80x9d state to a second logic xe2x80x9c1xe2x80x9d state without having to transition through a logic xe2x80x9c0xe2x80x9d state or from a first logic xe2x80x9c0xe2x80x9d state to a second logic xe2x80x9c0xe2x80x9d state without having to transition through a logic xe2x80x9c1xe2x80x9d state.
The above described approach benefits a very large scale integration (VLSI) architecture that implements a logical XOR function to compare multiple bits, for example a tag comparison inside a cache. In this manner, the VLSI architecture can perform an age comparison of registers associated with the VLSI architecture without having to add additional down stream logic elements to mitigate the effects of the XOR function hazard. Hence, a circuit designer or system architect is provided with greater design freedom, to implement faster and more robust logic circuits.
In yet another embodiment of the present invention, an XOR circuit that is free of the XOR function hazard is provided. The XOR circuit includes an encoder circuit that encodes a plurality of input values. For example, a first input value asserted on a first input node of the encoder circuit and a second input value asserted on a second input node of the encoder circuit into a first output value pair and a second output value pair, respectively. The first output value pair and the second output value pair are asserted on the inputs of an XOR circuit that performs a logical XOR function on the two output value pairs.
The two or more output value pairs are provided to the XOR circuit with three valid states to avoid the XOR function hazard. The three valid states of the plurality of output value pairs include a pre-charge state, a false state and a true state. The encoder circuit utilizes an implied inversion technique within the encoder circuit to encode each input value into their corresponding output value pairs. Each output value pair is a complementary dual-rail domino output signal.
The XOR circuit is configured as a dual-rail dynamic logic circuit without a series evaluate transistor having a plurality of first pull-down stacks and a plurality of second pull-down stacks coupled in parallel between a ground node and a dynamic node. Each first pull-down stack and each second pull-down stack perform a logical XOR function on a first output value pair and a second output value pair.
The above described approach benefits a microprocessor architecture that processes data in that physical registers awaiting retirement can be retired in a quicker more efficient manner. As a result, microprocessor processing efficiency is increased.